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JZ4730 32 Bits Microprocessor
Data Sheet
Revision: 1.1 Date: Aug. 2006
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JZ4730 32 Bits Microprocessor
Data Sheet
Copyright (c) Ingenic Semiconductor Co. Ltd 2006. All rights reserved.
Release history Date Apr. 2006 Aug. 2006 Revision 1.0 1.1 First release Change ball assignment and some DC parameter tables Add solder process description Change
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the usage, or intellectual property right infringement except as provided for by Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice. Anyone relying on this documentation should contact Ingenicfor the current documentation and errata.
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Content
Content 1 Overview............................................................................................ 3
1.1 1.2 Block Diagram......................................................................................................................... 3 Features .................................................................................................................................. 4 JzRISC Core ................................................................................................................... 4 System Control and Timers ............................................................................................. 4 Memory Interface ............................................................................................................ 4 Inter-chip Connectivity..................................................................................................... 5 Connectivity and Expansion ............................................................................................ 6 Multimedia Interface ........................................................................................................ 6 Clock and Power Management ....................................................................................... 7
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7
2 Packaging and Pinout Information..................................................... 8
2.1 2.2 2.3 2.4 2.5 Overview ................................................................................................................................. 8 Solder Process........................................................................................................................ 8 Package .................................................................................................................................. 9 Pin Description...................................................................................................................... 10 Ball Assignment .................................................................................................................... 21
3 Electrical Specifications ................................................................... 29
3.1 DC Specifications.................................................................................................................. 29 Absolute Maximum Ratings .......................................................................................... 29 Recommended operating conditions............................................................................. 30 Power Consumption Specifications............................................................................... 32 3.1.1 3.1.2 3.1.3 3.2 3.3
AC Specifications .................................................................................................................. 33 Oscillator Electrical Specifications ........................................................................................ 34 32.768KHz Oscillator Specifications ............................................................................. 34 3.6864MHz Oscillator Specifications............................................................................. 34 Power-On Timing........................................................................................................... 35 Hardware Reset Timing................................................................................................. 36
3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.6
Reset and Power AC Timing Specifications.......................................................................... 35
Memory Bus and PCMCIA AC Specifications ....................................................................... 37 Peripheral Module AC Specifications.................................................................................... 37 LCD Module Timing....................................................................................................... 37 CIM Module Timing ....................................................................................................... 37 SPI Module Timing ........................................................................................................ 37 External DMA Request and Grant................................................................................. 37
3.6.1 3.6.2 3.6.3 3.6.4
i JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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ii JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Overview
1 Overview
JZ4730 is a 32 Bits RISC processor targeting for handheld and general embedded applications. Incorporate the JzRISC core based on leading micro architecture technology, this processor provides high integration, high performance and low power consumption solution for embedded device. The JzRISC is the advanced and power-efficient 32-bit RISC core with 16K I-Cache and 16K D-Cache in this processor, operating at speeds up to 400MHz. On-chip modules such as LCD controller, AC97/I2S controller and camera interface offer designers a rich suite of peripherals for multimedia application. The memory interface supports a variety of memory types that allow flexible design requirements, include the glueless connection to NAND Flash for cost sensitive applications. WLAN, Bluetooth and expansion options are provided through the PCMCIA/CF, USB, and MMC/SD host controllers. And the other peripherals such as UART, SPI, and Ethernet controller as well as general-system resources provide enough compute and connectivity capability for many applications. For the processor block diagram, refer to .
1.1
Block Diagram
3.68MHz
Clock Divider GPIO PWM I2C SPI/SSP/uWire UART *4 IrDa Smart Card*2 AC97/I2S MMC/SD
Core PLL Clock/Power Interrupt OS Timer Watch Dog RTC A P B AHB JzRISC * 400MHz * 16K+16K
JTAG
Ethernet MAC USB 1.1 Host USB 1.1 Device LCD Controller CCIR656 In/Out
External Memory Controller
SRAM Controller SDRAM Controller NandFlash Controller PCMCIA/CF Controller
Figure 1-1 JZ4730 Diagram
3 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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1.2
1.2.1
Features
JzRISC Core
JzRISC core is a high performance and low power microprocessor core. * * * * * 32-bit RISC CPU, clock up to 400MHz Low power consumption: < 0.5mW/MHz 16K I-Cache & 16K D-Cache MMU support with I-TLB, D-TLB and J-TLB Hardware Debug support via JTAG port
1.2.2
System Control and Timers
* Interrupt controller * * Total 28 maskable interrupt sources from on-chip peripherals and external request through GPIO ports Interrupt source and pending registers for software handling Unmasked interrupts can wake up the chip in sleep or standby mode Provide three separate channels 32-bit counter with auto-reload function Generate interrupt when the down counter underflows Six counting clock sources: RTCCLK (real time clock), EXTAL (external clock input), /4, /16, /64 and /256. ( is the internal clock for on-chip peripheral) Watchdog timer * * 32-bit counter with RTC clock Generate power-on reset Period control through a 6-bit clock divider and a 10-bit period counter 10-bit pulse counter Total GPIO pin number is 128 Each pin can be configured as general-purpose input or output or multiplexed with internal chip functions Each pin can act as a interrupt source and has configurable rising/falling edge or high/low level detect manner, and can be masked independently Each pin can be configured as open-drain when output
Operating system timer
Pulse Width Modulator (PWM)
General-Purpose I/O ports
1.2.3
Memory Interface
* Static memory interface Direct interface to SRAM, ROM, Burst ROM, and NOR Flash
4 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Overview
* * * * *
Six chip-select pin for static memory, each can be configured separately Support 8, 16 or 32 bits data width The size and base address of static memory banks are programmable Support on CS3, sharing with static memory bank 3 Support all 8-bit/16-bit NAND Flash devices regardless of density and organization Hardware ECC generation Support automatic boot up from NAND Flash devices 2 banks with programmable size and base address 32-bit and 16-bit data bus width is supported Multiplexes row/column addresses according to SDRAM capacity Two-bank or four-bank SDRAM is supported Supports auto-refresh and self-refresh functions Supports power-down mode to minimize the power consumption of SDRAM Supports page mode Fully compliant with the release of March 1997 of PC Card standard (16-bit PC Card) DMA transfer support Supports two PCMCIA or CF socket Eight independent DMA channels Transfer data units: 8-bit, 16-bit, 32-bit, 16-byte or 32-byte Transfer requests can be: auto-request within DMA; on-chip peripheral module request; and external request Interrupt on transfer completion or transfer error Supports two transfer modes: single mode or block mode
NAND Flash interface
Synchronous DRAM Interface
PC Card Interface
Direct Memory Access Controller
The JZ4730 processor system supports little endian only
1.2.4
Inter-chip Connectivity
* I2C bus interface * Only supports single master mode Supports I2C standard-mode and F/S-mode up to 400 kHz Double-buffered for receiver and transmitter Supports general call address and START byte format after START condition Supports three formats: TI's SSP, National Microwire, and Motorola's SPI Configurable 2 - 17 (or multiples of them) bits data transfer Full-duplex/transmit-only/receive-only operation Supports normal transfer mode or Interval transfer mode Programmable transfer order: MSB first or LSB first 17-bit width, 16-level deep transmit-FIFO and receive-FIFO
5
Synchronous serial interface
JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Programmable divider/prescaler for SSI clock Back-to-back character transmission/reception mode
1.2.5
Connectivity and Expansion
* Four UART interface * * * 5, 6, 7 or 8 data bit operation with 1 or 1.5 or 2 stop bits, programmable parity (even, odd, or none) 16x8bit FIFO for transmit and 16x11bit FIFO for receive data Programmable baud rate up to 230.4Kbps Interrupt support for transmit, receive (data ready or timeout), and line status Supports DMA transfer mode Provide complete serial port signal for modem control functions Support slow infrared asynchronous interface (IrDA) Compliant with ISO/IEC standard 7816-3, supports both normal smart card and UIM card interface Support asynchronous character (T = 0)/ block (T = 1) communication modes 8-bit, 16-level FIFO, and programmable SCC_CLK output clock frequency Interrupt support for data communication and error handling Open Host Controller Interface (OHCI)-compatible and USB Revision
Two smart card controller
USB host interface 1.1-compatible USB device interface Compliant with USB protocol revision 1.1 Supports suspend/resume and remote wakeup Supports 8 physical endpoints and 9 logic endpoints Supports bulk, isochronous, interrupt and control transaction Compliant with IEEE802.3, 802.3u 10/100 Mbps data transfer rates with full and half duplex modes IEEE802.3 compliant MII interface to talk to an external PHY VLAN support 2K bytes Tx buffers, and 2K bytes Rx buffers Supports DMA engine using burst mode Supports remote wake-up frame and magic packet frame
*
Ethernet MAC interface
1.2.6
Multimedia Interface
* LCD Single-panel display in active mode, and single- or dual-panel displays in passive mode Up to 64K colors in active mode, and up to 4096 colors in passive mode Display size up to 800x600 pixels
6 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Overview
* * *
256x16 bits internal palette RAM Support ITU601/656 data format Supports 16, 18 and 20 bit sample for AC-link format, and 8, 16, 18, 20 and 24 bit for I2S/MSB-Justified format DMA transfer mode support Programmable Output channels and Input channels or Fixed mode for AC-link format Power down mode and two wake-up mode support for AC-link format Programmable Interrupt function support Input image size up to 2048x2048 pixels Supports CCIR656 data format 32x32 image data receive FIFO with DMA support Compliant with "The MultiMediaCard System Specification version 3.3" Compliant with "SD Memory Card Specification version 1.01" and "SDIO Card Specification version 1.0" with 1 command channel and 4 data channels 20~80 Mbps maximum data rate Supports up to 10 cards (including one SD card) Maskable hardware interrupt for SD I/O interrupt, internal status, and FIFO status
AC97/I2S controller
Camera interface
MultiMedia Card/Secure Digital Controller
1.2.7
Clock and Power Management
* Clock generation Module * On-chip 3.6864MHz oscillator circuit One On-chip phase-locked loops (PLL) with programmable multiple-ratio. Internal counter are used to ensure PLL stabilize time PLL on/off is programmable by software ICLK, PCLK, SCLK, MCLK and LCLK frequency can be changed separately for software by setting division ratio Power Manager Supports six low-power modes and function: NORMAL mode; DOZE mode; IDLE mode; SLEEP mode; HIBERNATE mode; and MODULE-STOP function.
7 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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2 Packaging and Pinout Information
2.1 Overview
JZ4730 processor is packaged in a 256-pin ball grid array (LFBGA), has a square 17x17 and 4 rows ball assignment. The following figures and tables list all the functional pins. Most of the GPIO pins are multiplexed on the on-chip peripheral modules, and the reset state is general-purpose input with internal pull-up or pull-down.
2.2
Solder Process
JZ4730 package is lead-free. It's reflow profile follows the IPC/JEDEC lead-free reflow profile as contained in J-STD-020C.
8 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
2.3
Package
Top View
Side View
Notes: 1. Bottom View 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C Primary datum C and seating plane are defined by the spherical crowns of the solder balls
5 6
3. Package outline - 20 x 20 matrix, 17.00mm x 17.00mm x 1.40mm, 0.70mm mold cap, 0.46mm ball, 0.80mm pitch, laminate substrate
Figure 2-1 JZ4730 package
9 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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2.4
Pin Description
D [31:0] A [25:0] DCS0_ DCS1_ / GP82 RAS_ CAS_ CKE CKO RDWR_ MSC_DAT [3:0] / GP37~34 MSC_CMD / GP38 MSC_CLK / GP39 BITCLK / GP77 SDATA_IN / GP71 SDATA_OUT / GP70 SYNC / GP78 SYSCLK / GP68 ACRESET_ / GP69 CIM_D [7:0] / GP7~0 CIM PCLK / GP10 CIM_MCLK / GP11 / TP4 CIM_HSYNC / GP9 CIM_VSYNC / GP8 PWM0 / GP94 PWM1 / GP95 TDO TDI TMS
MSC / GPIO signals
AIC / GPIO signals
Memory bus / GPIO signals
CS0 CS_ [5:1] / GP87~83 RD_ / POE_ WE_ / PWE_ WE0_ / PIOW_ WE1_ / PIOR_ WE2_ / REG_ WE3_ WAIT_ / PWAIT_ FRE_ / GP79 FEW_ / GP80 RB_ / GP81 IOIS16_ / GP92/TP[3] PSKTSEL / GP91/TP[2] PCE1_ / GP90/TP[1]
CIM / GPIO signals
PWM / GPIO signals
JZ4730 [256 pins] (1)
TCK TRSTN_ TAP_MD BOOTSEL[3:0] TEST_MODE RESETP_ RTCCLK RESETOUT_ EXTAL 1~0 XTAL 1~0
JTAG
PCMCIA / CF / GPIO signals
PCE2_ / GP93/TP[0] INPACK_ / GP88 PBVD2 / GP89 SDA
System
I2C
SCK
Figure 2-2 JZ4730 Pin Diagram (1)
10 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
LCD_D [15:8] / GP55~48 / TP_MD [17:10] LCD_D [7:0] / GP47~40 LCD VSYNC / GP56 LCD_HSYNC / GP57 LCD_PCLK / GP58
UART3_RTS_ / GP23/TP[8] UART3_CTS# / GP17 UART3_TxD / GP21 UART3_RxD / GP16 UART2_TxD / GP125 UART2_RxD / GP111
LCD / GPIO signals
UART3 / GPIO signals
LCD_DE / GP59 LCD_SPL / GP60 LCD_CLS / GP61 LCD_PS / GP62 LCD_REV / GP63 MII_COL / GP115 MII_CRS / GP116 DREQ0 / GP12 MII_TX_CLK MII_TXD [3:0] / GP120~117 AEN / GP26 MII_TX_EN / GP112 EOP / GP27 DACK0 / GP13 UART1_TxD / GP25 UART1_RxD / GP24 UART0_TxD / GP127 UART0_RxD / GP126
UART2 / UART1 / UART0 / GPIO signals
DMA / GPIO signals
MAC/GPIO signals
MII RX CLK MII_RX_DV / GP113
MII_RXD [3:0] / GP124~121 MII_RX_ER / GP114 MII_MDC MII MDIO USB_CLK / GP28 DPLS0 DMNS0 PPWR0 / GP29
SCC0_DATA / GP64 SCC1_DATA / GP65 SCC0_CLK / GP66 SCC1_CLK / GP67
SCC / GPIO signals
JZ4730(R) [256 pins] (2)
SSI_CLK / GP72 SSI_CE1_ / GP73 SSI_DT / GP74 SSI_DR / GP75
UHC / GPIO signals
OVC0 / TEST_SEN DPLS1 DMNS1
SSI / GPIO signals
SSI_CE2_ / TP[9] / SPI_GPC / GP76 VDD/VSScore VDD/VSS (IO1) VDD/VSS (IO2)
GPIO signals PS2 / GPIO signals
GP110~96 PS2_KCLK / GP32 PS2_KDATA / GP33
Supply
Figure 2-3 JZ4730 Pin Diagram (2)
11 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Table 2-1 EMC Pins (81 for 256; 9 GPIO) Pin Name D[31:16] D[15:0] A[25:17] A[16:2] A[1:0] DCS0_ DCS1 / GP82 RAS_ CAS_ CKE RDWR_ CKO CS0_ CS1_ / GP83 CS2_ / GP84 CS3_ / GP85 CS4_ / GP86 CS5_ / GP87 RD_ / POE_ WE_ / PWE_ WE0_ / PIOW_ WE1_ / PIOR_ WE2_ / PREG_ WE3_ WAIT_ / PWAIT_ Type I/O I/O Output Output Output Output I/O Output Output Output Output Output Output I/O I/O I/O I/O I/O Output Output Output Output Output Output Input Description Memory data bus, used for 32-bit memories Memory data bus, lower 16 bits of the data bus Static memory address SDRAM memory address, multiplexing static memory address Static memory address SDRAM chip select 0 SDRAM chip select 1 / GPIO 82 Row address strobe for SDRAM Column address strobe for SDRAM Clock enable for SDRAM Read/write signal, 1 - read; 0 - write SDRAM clock Static memory bank 0 chip select Static memory bank 1 chip select / GPIO 83 Static memory bank 2 chip select / GPIO 84 Static memory bank 3 chip select / GPIO 85 Static memory bank 4 chip select / GPIO 86 Static memory bank 5 chip select / GPIO 87 Read strobe for static memory device / Pcmcia memory read strobe Write strobe for static memory device / Pcmcia memory write strobe Byte 0 write enable / pcmcia IO write strobe Byte 1 write enable / pcmcia IO read strobe Byte 2 write enable / pcmcia register select Byte 3 write enable Wait signal for slow memory / pcmcia wait input Internal pull-up Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Comments
12 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
FRE_ / GP79 FWE_ / GP80 FRB_ / GP81
I/O I/O I/O
Read enable for NAND Flash / GPIO 79 Write enable for NAND Flash / GPIO 80 Ready or busy signal for NAND Flash / GPIO 81
Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-2 PCMCIA/CF Pins (6 for 256; 6 GPIO) Pin Name IOIS16_ / GP92 / TP[3] PSKTSEL / GP91 / TP[2] PCE1_ / GP90 / TP[1] PCE2_ / GP93 / TP[0] INPACK_ / GP88 PBVD2 / GP89 I/O I/O I/O I/O I/O I/O Type GPIO 92 / Test port [3] PCMCIA socket select / GPIO 91 / Test port [2] PCMCIA card enable 1 / GPIO 90 / Test port [1] PCMCIA card enable 2 / GPIO 93 / Test port [0] PCMCIA INPACK_ input / GPIO 88 PCMCIA BVD2 input / GPIO89 Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Description PCMCIA IO address 16 bit select / Comments Pull-up input at reset
Table 2-3 LCD Pins (24 for 256; 24 GPIO) Pin Name LCD_D[15:8] / GP55 ~ GP48 / TP[17:10] LCD_D[7:0] / GP47 ~ GP40 LCD_VSYNC / GP56 LCD_HSYNC / GP57 LCD_PCLK / GP58 LCD_DE / GP59 I/O I/O I/O I/O I/O I/O Type Description Higher 8-bit of LCD data / GPIO 55 ~ GPIO 48 / Test port [17:10] Lower 8-bit of LCD data / GPIO 47 ~ GPIO 40 LCD frame clock/vertical sync / GPIO 56 LCD line clock/horizonal sync / GPIO 57 LCD pixel clock / GPIO 58 STN AC bias drive/Non-STN data enable output / GPIO 59 Pull-up input at reset Pull-down input at reset Pull-up input at reset Pull-down input at reset Pull-down input at reset
13 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
Comments Pull-down input at reset
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LCD_SPL / GP60 LCD_CLS / GP61 LCD_PS / GP62 LCD_REV / GP63
I/O I/O I/O I/O
LCD SPL output for special TFT panel / GPIO 60 LCD CLS output for special TFT panel / GPIO 61 LCD PS output for special TFT panel / GPIO 62 LCD REV output for special TFT panel / GPIO 63
Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-4 I2C Pins (2 for 256) Pin Name I2C_SDA I2C_SCK Type I/O I/O I2C serial data I2C serial clock Description Comments Open drain Open drain
Table 2-5 SCC Pins (4 for 256; 4 GPIO) Pin Name SCC0_DATA / GP64 SCC0_CLK / GP66 SCC1_DATA / GP65 SCC1_CLK / GP67 Type I/O I/O I/O I/O SCC0 data / GPIO 64 SCC0 clock / GPIO 66 SCC1 data / GPIO 65 SCC1 clock / GPIO 67 Description Comments Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-6 UART3 Pins (4 for 256; 8 GPIO) Pin Name UART3_CTS_ / GP17 UART3_RTS_ / GP23 / TP[8] UART3_TxD_ / GP21 UART3_RxD_ / GP16 I/O I/O I/O Type I/O GPIO 17 UART3 request to send / GPIO 23 / Test port [8] UART3 TxD / GPIO 21 UART3 RxD / GPIO 16 Pull-up input at reset Pull-up input at reset Description UART3 clear to send / Comments Pull-up input at reset Pull-up input at reset
Table 2-7 UART2 Pins (2 for 256; 2 GPIO)
14 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Pin Name UART2_TxD_ / GP125 UART2_RxD_ / GP111
Type I/O I/O UART2 TxD / GPIO 125 UART2 RxD / GPIO 111
Description
Comments Pull-up input at reset Pull-up input at reset
Table 2-8 UART1 Pins (2 for 256; 2 GPIO) Pin Name UART1_TxD_ / GP25 UART1_RxD_ / GP24 Type I/O I/O UART1 TxD / GPIO 25 UART1 RxD / GPIO 24 Description Comments Pull-up input at reset Pull-up input at reset
Table 2-9 UART0 Pins (2 for 256; 2 GPIO) Pin Name UART0_TxD_ / GP127 UART0_RxD_ / GP126 Type I/O I/O UART0 TxD / GPIO 127 UART0 RxD / GPIO 126 Description Comments Pull-up input at reset Pull-up input at reset
Table 2-10 SSI Pins Pin Name SSI_CLK / GP72 SSI_CE1_ / GP73 SSI_DT / GP74 SSI_DR / GP75 SSI_CE2_ / SPI_GPC / GP76 / TP[9] I/O Type I/O I/O I/O I/O SSI clock output / GPIO 72 SSI chip enable 1 / GPIO 73 SSI data output / GPIO 74 SSI data input / GPIO 75 SSI chip enable 2 / SSI GPC / GPIO 76 / Test port [9]
(5 for 256; 5 GPIO) Description Comments Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-11 DMA Pins (4 for 256; 6 GPIO) Pin Name DREQ0 / GP12 Type IO GPIO 12 Description DMA external request 0 / Comments Pull-up input at reset
15 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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DACK0 / GP13 AEN / GP26 / TP[5] EOP / GP27 / TP[6]
IO
DMA transfer acknowledge 0 / GPIO 13 Address enable for transfer / GPIO 26 / Test port [5] DMA transfer end /
Pull-up input at reset Pull-up input at reset Pull-up input at reset
IO
IO
GPIO 27 / Test port [6]
Table 2-12 PWM Pins (2 for 256; 2 GPIO) Pin Name PWM0 / GP94 PWM1 / GP95 Type I/O I/O PWM 0 output / GPIO 94 PWM 1 output / GPIO 95 Description Comments Pull-up input at reset Pull-up input at reset
Table 2-13 UHC Pins (7 for 256; 4 GPIO) Pin Name USB_CLK / GP28 DPLS0 DMNS0 OVC0 / TEST_SEN PPWR0 / GP29 DPLS1 DMNS1 Type I/O Analog I/O Analog I/O I I/O Analog I/O Analog I/O GPIO 28 USB transceiver data plus 0 USB transceiver data minus 0 Overcurrent input 0 / Scan enable for scan-req Power enable output 0 / GPIO 29 USB transceiver data plus 1 USB transceiver data minus 1 Pull-up input at reset Description USB 48MHz clock / Comments Pull-up input at reset
Table 2-14 MAC Pins (17 for 256; 13 GPIO) Pin Name MII_COL / GP115 MII_CRS / GP116 Type I/O I/O Ethernet collision / GPIO 115 Ethernet carrier sense / GPIO 116 Description Comments Pull-up input at reset Pull-up input at reset
16 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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MII_TX_CLK MII_TXD[3] / GP120 MII_TXD[2] / GP119 MII_TXD[1] / GP118 MII_TXD[0] / GP117 MII_TX_EN / GP112 MII_RX_CLK MII_RX_DV / GP113 MII_RXD[3] / GP124 MII_RXD[2] / GP123 MII_RXD[1] / GP122 MII_RXD[0] / GP121 MII_RX_ER / GP114 MII_MDC MII_MDIO
Input I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O Output I/O
Ethernet transmit clock Ethernet transmit data / GPIO 120 Ethernet transmit data / GPIO 119 Ethernet transmit data / GPIO 118 Ethernet transmit data / GPIO 117 Ethernet transmit enable / GPIO 112 Ethernet receive clock Ethernet receive data valid / GPIO 113 Ethernet receive data / GPIO 124 Ethernet receive data / GPIO 123 Ethernet receive data / GPIO 122 Ethernet receive data / GPIO 121 Ethernet receive error / GPIO 114 Ethernet management clock Ethernet management data inout Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-15 CIM Pins (12 for 256; 12 GPIO) Pin Name CIM_D [7:0] / GP7 ~ GP0 CIM_PCLK / GP10 CIM_MCLK / GP11 / TP[4] CIM_HSYNC / GP9 CIM_VSYNC / GP8 I/O I/O I/O Type I/O I/O GPIO 7 ~ GPIO 4 CIM pixel clock / GPIO 10 CIM master clock / GPIO 11 / Test port [4] CIM horizontal clock / GPIO 9 CIM vertical clock / GPIO 8 Pull-up input at reset Pull-up input at reset Description Data input from image sensor / Comments Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-16 PS2 Keyboard Pins (2 for 256; 2 GPIO)
17 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Pin Name PS2_KCLK / GP32 PS2_KDATA / GP33
Type I/O I/O GPIO 32
Description PS/2 keyboard clock / PS/2 keyboard data / GPIO 33
Comments Pull-up input at reset Pull-up input at reset
Table 2-17 AC97/I2S Pins (6 for 256; 6 GPIO) Pin Name BITCLK / GP77 SDATA_IN / GP71 SDATA_OUT / GP70 SYNC / GP78 SYSCLK / GP68 ACRESET_ / GP69 Type I/O I/O I/O I/O I/O I/O GPIO 77 AIC serial data input / GPIO 71 AIC serial data output / GPIO 70 AIC frame synchronization pin / GPIO 78 AIC system clock output / GPIO 68 AIC reset output / GPIO 69 Description AIC serial clock pin / Comments Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-18 MSC Pins (6 for 256; 6 GPIO) Pin Name MSC_DAT[3] / GP37 MSC_DAT[2] / GP36 MSC_DAT[1] / GP35 MSC_DAT[0] / GP34 MSC_CMD / GP38 MSC_CLK / GP39 Type I/O I/O I/O I/O I/O I/O MSC data / GPIO 37 MSC data / GPIO 36 MSC data / GPIO 35 MSC data / GPIO 34 MSC command / GPIO 38 MSC clock output / GPIO 39 Description Comments Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset Pull-up input at reset
Table 2-19 GPIO Pins (15 for 256;) Pin Name Type Description Comments
18 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
GP110 ~ GP96
I/O
Special GPIO 110 ~ GPIO 96
Pull-up input at reset
Table 2-20 JTAG Pins (5 for 256) Pin Name TRSTN_ TMS TDI TCK TDO Type Input Input Input Input Output JTAG reset JTAG mode select JTAG serial data input JTAG clock JTAG serial data output Description Comments Internal pull-down Internal pull-up Internal pull-up Internal pull-down
Table 2-21 System Pins (11 for 256) Pin Name EXTAL XTAL RTCCLK RESETOUT_ RESETP_ BOOT_SEL[3] Type Analog Input Analog Output Input Output Input Input System clock input OSC output RTC clock input Reset output System power on reset input Boot select input 3: 0->boot from ROM at CS0; 1->boot from NAND flash device at CS3 Boot select input 2: BOOT_SEL[2] Input NAND flash address cycles when boot from it, 0->low cycle; 1->high cycle Boot_select input 1: BOOT_SEL[1] Input NAND flash page size when boot from it, 0->512B; 1->2048B Boot select input 0: BOOT_SEL[0] Input NAND flash width when boot from it, 0->8bit; 1->16bit TEST_MODE TAP_MD Input Input Chip test mode TAP mode input - (1: internal JTAG; 0: boundary) Internal pull-down Internal pull-down
19 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
Description
Comments
Internal pull-down Internal pull-down
Internal pull-down
Internal pull-down
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Table 2-22 Power Pins (28 for 256) Pin Name VDDIO1 VSSIO1 VDDIO2 VSSIO2 VDDcore VSScore VDDPLL VSSPLL VDDUSB VSSUSB Ground supply for IO pad (0V) Power supply for IO pad (3.3V) Ground supply for IO pad (0V) Power supply for core (1.8V) Ground supply for core (0V) PLL power supply for analog (1.8V) PLL ground supply for analog Power supply for USB IO pad (3.3V) Ground supply for USB IO pad (0V) Description Power supply for IO pad (1.8V ~ 3.3V)
20 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
2.5
Ball Assignment
Table 2-23 Ball and IO cell description1, 2, 3
Ball#
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
Signal Name
MII_TX_CLK MII_MDC MII_RX_ER/GP114 MII_RX_CLK AEN/GP26 VDDIO1 CS5_/GP87 CS2_/GP84 WAIT_ A[0] A[18] A[22] A[25] CKO WE0_ D[2] D[6] D[9] D[11] D[12] MII_MDIO MII_TXD1/GP118 MII_RXD2/GP123 MII_CRS/GP116 DREQ0/GP12 DACK0/GP13 FWE_/GP80 CS3_/GP85 CS0_ RD_ A[17] A[21] A[24] DCS0_ RAS_ D[1] D[5]
I/O IO Cell
I O IO I IO P IO IO I O O O O O O IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O IO IO I T02 UW02 I UW02 2mA out
IO Cell Characteristics
Power Note
VDDIO2 VDDIO2 VDDIO2 VDDIO2
2mA out, pull-up, pull-up on/off
2mA out, pull-up, pull-up on/off -
VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1
MUW02 2mA out, pull-up, pull-up on/off MUW02 2mA out, pull-up, pull-up on/off MUS MO02 MO02 MO02 MO02 MT12 MO08 MB08 MB08 MB08 MB08 MB08 B02 UW02 UW02 UW02 UW02 UW02 UW02 Pull-up, Schmitt 2mA out 2mA out 2mA out 2mA out 12mA out 8mA out 8mA out 8mA out 8mA out 8mA out 8mA out 2mA out 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off
MUW02 2mA out, pull-up, pull-up on/off MT02 MT02 MO02 MO02 MO02 MO08 MO08 MB08 MB08 2mA out 2mA out 2mA out 2mA out 2mA out 8mA out 8mA out 8mA out 8mA out
21 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Ball#
B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
Signal Name
D[8] D[10] D[13] LCD_D[14]/GP54 MII_TXD0/GP117 MII_TXD3/GP120 MII_RXD0/GP121 MII_RX_DV/GP113 EOP/GP27 FRE_/GP79 CS4_/GP86 CS1_/GP83 WE_ A[1] A[20] A[23] DCS1_/GP82 CAS_ D[0] D[4] D[7] D[14] D[15] LCD_D[10]/GP50 LCD_D[12]/GP52 MII_TX_EN/GP112 MII_RXD1/GP122 MII_COL/GP115 VSSIO2 FRB_/GP81 VDDIO1 VSSIO1 VDDcore VSScore A[19] VSSIO1 VDDIO1 CKE WE1_
I/O IO Cell
IO IO IO IO IO IO IO IO IO IO IO IO O O O O IO O IO IO IO IO IO IO IO IO IO IO P IO P P P P O P P O O MB08 MB08 MB08 DW04 UW02 UW02 UW02 UW02 UW02 UW02 8mA out 8mA out 8mA out
IO Cell Characteristics
Power Note
VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1
4mA out, pull-down, pull-down on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off
MUW02 2mA out, pull-up, pull-up on/off MUW02 2mA out, pull-up, pull-up on/off MT02 MO02 MO02 MO02 2mA out 2mA out 2mA out 2mA out
MUW08 8mA out, pull-up, pull-up on/off MO08 MB08 MB08 MB08 MB08 MB08 DW04 DW04 UW02 UW02 UW02 8mA out 8mA out 8mA out 8mA out 8mA out 8mA out 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off -
MUW04 4mA out, pull-up, pull-up on/off MO02 MO08 MO08 2mA out 8mA out 8mA out
22 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
Ball#
D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17
Signal Name
D[3] RDWR_ WE2_ WE3_ LCD_D[7]/GP47 LCD_D[13]/GP53 LCD_D[15]/GP55 MII_RXD3/GP124 A[2] A[3] A[4] A[5] LCD_D[6]/GP46 LCD_D[9]/GP49 LCD_D[11]/GP51 MII_TXD2/GP119 A[6] A[7] A[8] A[9] LCD_D[2]/GP42 LCD_D[4]/GP44 LCD_D[8]/GP48 VSSIO2 A[10] A[11] A[12] A[13] LCD_PCLK/GP58 LCD_D[1]/GP41 LCD_D[5]/GP45 VDDIO2 VSSIO1 A[14] A[15] A[16] LCD_VSYNC/GP56 LCD_HSYNC/GP57 LCD_D[0]/GP40 LCD_D[3]/GP43 VDDIO1
I/O IO Cell
IO O O O IO IO IO IO O O O O IO IO IO IO O O O O IO IO IO P O O O O IO IO IO P P O O O IO IO IO IO P MB08 MOL12 MO08 MO08 DW04 DW04 DW04 UW02 MOL12 MOL12 MOL12 MOL12 DW04 DW04 DW04 UW02 MOL12 MOL12 MOL12 MOL12 UW04 DW04 DW04 MOL12 MOL12 MOL12 MOL12 DW04 UW04 DW04 MOL12 MOL12 MOL12 DW04 UW04 UW04 DW04 8mA out 12mA out 8mA out 8mA out
IO Cell Characteristics
Power Note
VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 -
4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 2mA out, pull-up, pull-up on/off 12mA out 12mA out 12mA out 12mA out 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 2mA out, pull-up, pull-up on/off 12mA out 12mA out 12mA out 12mA out 4mA out, pull-up, pull-up on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 12mA out 12mA out 12mA out 12mA out 4mA out, pull-down, pull-down on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-down, pull-down on/off 12mA out 12mA out 12mA out 4mA out, pull-down, pull-down on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off -
23 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Ball#
J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4
Signal Name
D[16] D[17] D[18] LCD_CLS/GP61 LCD_SPL/GP60 LCD_DE/GP59 VSScore VDDcore D[19] D[20] D[21] LCD_PS/GP62 LCD_REV/GP63 TAP_MD VDDcore VSScore D[22] D[23] D[24] CIM_D[0]/GP0 CIM_D[1]/GP1 CIM_D[2]/GP2 CIM_D[3]/GP3 D[25] D[26] D[27] D[28] CIM_D[4]/GP4 CIM_D[5]/GP5 CIM_D[6]/GP6 CIM_D[7]/GP7 D[29] D[30] D[31] IOIS16_ CIM_MCLK/GP11 CIM_PCLK/GP10 CIM_HSYNC/GP9 CIM_VSYNC/GP8
I/O IO Cell
IO IO IO IO IO IO P P IO IO IO IO IO I P P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MB08 MB08 MB08 UW04 UW04 DW04 MB08 MB08 MB08 UW04 UW04 IDS MB08 MB08 MB08 UW04 UW04 UW04 UW04 MB08 MB08 MB08 MB08 DW04 DW04 DW04 DW04 MB08 MB08 MB08 UW04 DW04 DW04 UW04 DW04 8mA out 8mA out 8mA out
IO Cell Characteristics
Power Note
VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2
4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-down, pull-down on/off 8mA out 8mA out 8mA out 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off Schmitt, pull-down 8mA out 8mA out 8mA out 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 8mA out 8mA out 8mA out 8mA out 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 8mA out 8mA out 8mA out 4mA out, pull-up, pull-up on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-down, pull-down on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-down, pull-down on/off
24 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
Ball#
P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3
Signal Name
VSSIO2 PCE2_/GP93 PCE1_/GP90 PSKTSEL/GP91 TEST_MD VDDcore USB_CLK/GP28 VSScore VDDIO1 INPACK_/GP88 PBVD2/GP89 UART0_TXD/GP127 OVC0 PPWR0/GP29 DPLS1
I/O IO Cell
P IO IO IO I P IO P P IO IO IO I IO IO UW04 UW04 UW04 IDS UW02 UW02 UW02 UW02 IS UW02 USB 1.1 PHY -
IO Cell Characteristics
4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off Schmitt, pull-down 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off Schmitt 2mA out, pull-up, pull-up on/off
Power Note
VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDusb
T4
DMNS1
IO
USB 1.1 PHY
VDDusb
T17 T18 T19 T20 U1
NC UART1_RXD/GP24 UART2_RXD/GP111 UART1_TXD/GP25 DPLS0
IO IO IO A IO
UW02 UW02 UW02 USB 1.1 PHY USB 1.1 PHY -
2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off
VDDIO2 VDDIO2 VDDIO2 VDDusb
U2
DMNS0
A IO
VDDusb
U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18
VSSusb NC XTAL TDO TRSTN_ SSI_DR/GP75 VDDIO2 VSSIO2 VDDcore VSScore GP99 GP108 MSC_CMD/GP38 MSC_DAT[1]/GP35 NC UART3_TXD/GP21
P -
Oscillator output 4mA out Schmitt, pull-down 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off
VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2
AO OSCO O I IO P P P P IO IO IO IO IO T04 IDS UW02 UW02 UW02 UW04 UW04 UW02
25 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Ball#
U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17
Signal Name
UART3_RXD/GP16 UART0_RXD/GP126 VDDusb VSSpll NC EXTAL I2C_SCK TCK BOOT_SEL[2] SSI_CE1_/GP73 SYSCLK/GP68 SYNC/GP78 PWM1/GP95 SCC0_DATA/GP64 GP103 GP98 GP109 GP105 MSC_DAT[3]/GP37 UART3_RTS_/GP23 NC UART2_TXD/GP125 VDDpll RTCCLK RESETP_ RESETOUT_ TDI BOOT_SEL[0] BOOT_SEL[1] SSI_DT/GP74 SDATA_OUT/GP70 ACRESET_/GP69 PS2_CLK/GP32 SCC0_CLK/GP66 SCC1_DATA/GP65 GP101 GP97 GP106 GP104
I/O IO Cell
IO IO P P AI O I I IO IO IO IO IO IO IO IO IO IO IO IO P I I O I I I IO IO IO IO IO IO IO IO IO IO UW02 UW02 OSCI B04 IDS IDS UW02 UW02 UW02 UW02 UW04 UW02 UW02 UW02 UW02 UW04 UW02 UW02 ICD IS O04 IUS IDS IDS UW02 UW02 UW02 UW02 UW04 UW04 UW02 UW02 UW02 UW02
IO Cell Characteristics
2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off Oscillator input 4mA out Schmitt, pull-down Schmitt, pull-down 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off Pull-down, pull-down on/off Schmitt 4mA out Schmitt, pull-up Schmitt, pull-down Schmitt, pull-down 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off
Power Note
VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2
26 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Packaging and Pinout Information
Ball#
W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 NC
Signal Name
MSC_DAT[0]/GP34
I/O IO Cell
IO IO O I I IO IO IO IO IO IO IO IO IO IO IO IO IO IO UW04 UW02 B04 IUS IDS UW02 UW02 UW02 UW02 UW04 UW02 UW04 UW02 UW02 UW02 UW02 UW02 UW04 UW04 -
IO Cell Characteristics
4mA out, pull-up, pull-up on/off
Power Note
VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2
UART3_CTS_/GP17 NC NC NC I2C_SDA TMS BOOT_SEL[3] SSI_CE2_/GP76 SSI_CLK/GP72 BITCLK/GP77 SDATA_IN/GP71 PWM0/GP94 PS2_DATA/GP33 SCC1_CLK/GP67 GP102 GP100 GP96 GP110 GP107 MSC_CLK/GP39 MSC_DAT[2]/GP36
2mA out, pull-up, pull-up on/off 4mA out Schmitt, pull-up Schmitt, pull-down 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 2mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off 4mA out, pull-up, pull-up on/off
Notes: 1. IO cells power supplied by VDDIO1 are regular IO cells. DC specification of them is described in Table 3-2 and Table 3-3 2. IO cells power supplied by VDDIO2 are standard IO cells. DC specification of them is described in Table 3-4 3. The meaning of phases in IO cell characteristics are a) b) c) d) e) f) 2/4/8/12mA out: The IO cell's output driving strength is about 2/4/8/12mA Pull-up: The IO cell contains a pull-up resistor Pull-down: The IO cell contains a pull-down resistor Pull-up on/off: The IO cell's pull-up resistor can be turned on or off by software. If this does not appear, the resistor is always on Pull-down on/off: The IO cell's pull-down resistor can be turned on or off by software. If this does not appear, the resistor is always on Schmitt: The IO cell is Schmitt trig input
27 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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28 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Electrical Specifications
3 Electrical Specifications
3.1 DC Specifications
The DC characteristics for each pin include input-sense levels and output-drive levels and currents. These parameters can be used to determine maximum DC loading, and also to determine maximum transition times for a given load. All DC specification values are valid for the entire temperature range of the device.
3.1.1
Absolute Maximum Ratings
The absolute maximum ratings for the processors are listed in Table 3-1. Do not exceed these parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not guaranteed.
Table 3-1 Absolute Maximum Ratings Symbol Tstg Topt Description Storage Temperature Operation Temperature VDDIO1 power supplies voltage VDDIO2 power supplies voltage VDDUSB power supplies voltage VDDcore power supplies voltage VDDPLL power supplies voltage VIIO1 VIIO2 VIUSB VOIO1 VOIO2 VOUSB Input voltage to VDDIO1 supplied non-supply pins Input voltage to VDDIO2 supplied non-supply pins Input voltage to VDDUSB supplied non-supply pins Output voltage from VDDIO1 supplied non-supply pins Output voltage from VDDIO2 supplied non-supply pins Output voltage from VDDUSB supplied non-supply pins Maximum ESD stress voltage, Human Body Model; VESD Any pin to any supply pin, either polarity, or Any pin to all non-supply pins together, either polarity. Three stresses maximum. 2000 V Min -65 -40 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 Max 125 125 4.6 4.6 4.6 2.5 2.5 4.6 6.0 6.0 4.6 4.6 4.6 Unit C C V V V V V V V V V V V
29 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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3.1.2
Recommended operating conditions
Table 3-2 Recommended operating conditions for VDDIO1 pins in 3.3V application Symbol VIO1 VIH VIL VT VT+ VTIL IOZ RPU RPD VOL VOH VDDIO1 voltage Input high voltage Input low voltage Threshold point Schmitt trig low to high threshold point Schmitt trig high to low threshold point Input Leakage Current Tri-State output leakage current Pull-up Resistor Pull-down Resistor Output low voltage @IOL=2, 4, 8, 12mA Output high voltage @IOH=2, 4, 8, 12mA Low level output current @VOL=0.4V for cells of 2mA IOL 4mA 8mA 12mA High level output current @VOH=2.4V for cells of 2mA IOH 4mA 8mA 12mA 2.5 5.0 10.0 15.0 5.1 10.2 20.4 30.6 7.9 15.9 31.7 47.6 mA 2.2 4.4 8.9 13.3 3.7 7.4 14.7 22.1 4.6 9.2 18.4 27.5 mA 2.4 50 40 65 56 Description Min 2.97 2.0 -0.3 1.46 1.44 0.88 1.59 1.50 0.94 Typical 3.3 Max 3.63 3.6 0.8 1.75 1.56 0.99 10 10 100 107 0.4 Unit V V V V V V A A k k V V
Table 3-3 Recommended operating conditions for VDDIO1 pins in 1.8V application Symbol VIO1 VIH VIL VT VT+ VTIL VDDIO1 voltage Input high voltage Input low voltage Threshold point Schmitt trig low to high threshold point Schmitt trig high to low threshold point Input Leakage Current Description Min 1.62 0.65 * VIO1 -0.3 0.87 0.95 0.56 0.92 0.99 0.58 Typical 1.8 Max 1.98 VIO1 + 0.3 0.35 * VIO1 0.98 1.00 0.60 10 Unit V V V V V V A
30 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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IOZ RPU RPD VOL VOH
Tri-State output leakage current Pull-up Resistor Pull-down Resistor Output low voltage @IOL=2, 4, 8, 12mA Output high voltage @IOH=2, 4, 8, 12mA Low level output current @VOL=0.4V for cells of 2mA 0.9 1.8 3.6 5.4 0.9 1.8 3.7 5.5 1.9 3.8 7.6 11.4 1.6 3.1 6.2 9.3 VIO1 - 0.45 94 77 148 135
10 261 312 0.45
A k k V V
3.0 6.0 12.0 18.0 2.2 4.5 9.0 13.4 mA mA
IOL
4mA 8mA 12mA High level output current @VOH=2.4V for cells of 2mA
IOH
4mA 8mA 12mA
Table 3-4 Recommended operating conditions for VDDIO2 pins Symbol VIO2 VIH VIL VT VT+ VTIL IOZ RPU RPD VOL VOH IOL VDDIO2 voltage Input high voltage Input low voltage Threshold point Schmitt trig low to high threshold point Schmitt trig high to low threshold point Input Leakage Current Tri-State output leakage current Pull-up Resistor Pull-down Resistor Output low voltage @IOL=2, 4mA Output high voltage @IOH=2, 4mA Low level output current @VOL=0.4V for cells of 2mA 4mA High level output current @VOH=2.4V for cells of IOH 2mA 4mA 2.8 5.6 5.9 11.9 9.5 19 mA 2.4 4.7 4.0 8.0 5.0 10.0 mA 2.4 39 40 65 56 Description Min 2.97 2.0 -0.3 1.45 1.44 0.88 1.58 1.50 0.94 Typical 3.3 Max 3.63 5.5 0.8 1.74 1.56 0.99 10 10 116 108 0.4 Unit V V V V V V A A k k V V
Table 3-5 Recommended operating conditions for VDDUSB pins Symbol Description Min Typical Max Unit
31 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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VUSB VILH VOLH VDI VCM VSE IOZ ZDRV VOL VOH
VDDUSB voltage Input voltage range Output voltage range Differential input sensitivity Differential common mode range Single ended receiver threshold Tri-State leakage current Driver output resistance, including damping resistor Static output low voltage Static output high voltage
2.97 0 0 0.2 0.8 0.8
3.3
3.63 VUSB VUSB 2.5 2.0 10
V V V V V V A V V
24
44 0.3
2.8
Table 3-6 Recommended operating conditions for others Symbol TA VCORE VPLL Description Ambient temperature Core voltage PLL analog voltage 0 1.62 1.62 1.8 1.8 Min Typical 70 1.98 1.98 Max Unit C V V
3.1.3
Power Consumption Specifications
Power consumption depends on the operating voltage, peripherals enabled, external switching activity, and external loading. The maximum power consumption specification is determined by all units running at their maximum: processor speed, voltage, and loading conditions. This method generates a conservative power consumption value; however, power supply and thermal management design requires the highest possible power consumption for robust design. The JZ4730 processor's maximum power consumption is calculated using the following conditions:
* * * *
All peripheral units operating at maximum frequency and size configuration All I/O loads maximum (50pF for Memory interface, 100pF for peripherals) Core operating at worst case power scenario (hit rates adjusted for worst power) All voltages at maximum of range
Do not exceed the maximum package power rating or Tcase temperature. But for most of applications, a more optimal system design requires more typical power-consumption figures. These figures are important when considering battery size and
32 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Electrical Specifications
optimizing regulator efficiency. Typical systems operate with fewer modules active and at nominal voltage and load. The typical power consumption for the JZ4730 processor is calculated using these conditions:
* *
All voltage at nominal value Nominal case temperature
Table 3-7 Power Consumption Specifications Symbol Description Typical Max Unit
400MHz normal mode; Maximum: V(core)= 2.2V, V(IO1)=V, V(IO2)=3.6V, Temp=100C Typical: V(core)=1.8V, V(IO1)=1.8V, V(IO2)=3.3V, Temp=Room mW mW mW mW mW mW mW mW mW
3.2
AC Specifications
A pin's AC Characteristics include input and output capacitance. These determine loading for external drivers or other load analysis. The AC Characteristics also include a de-rating factor, which indicates how much faster or slower the AC timings get with different loads. The AC Operating Conditions for all input, output, and I/O pins are shown in Table 3-8. All AC specification values are valid for entire temperature range of the device.
Table 3-8 Standard Input, Output, and I/O Pin AC Operating Conditions Symbol CIN COUT_G12 COUT_G8 NOTE: Description Input Capacitance, all input and IO pins Output Capacitance, 12mA output and IO pins Output Capacitance, 8mA SDRAM output and IO pins AC Specifications guaranteed for loads in this range. All testing is done at 50pF Min 3 Typical 5 Max 10 Units pF pF pF
33 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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3.3
Oscillator Electrical Specifications
The processor contains two oscillators, each for a specific crystal: a 32.768KHz oscillator and a 3.6864MHz oscillator. When choosing a crystal, match the crystal parameters as closely as possible.
3.3.1 3.3.2
32.768KHz Oscillator Specifications 3.6864MHz Oscillator Specifications
34 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Electrical Specifications
3.4
Reset and Power AC Timing Specifications
The JZ4730 processor asserts the RESETOUT_ pin in one of several modes:
* *
Power On Reset (RESETP_) Watch Dog Reset (internal controlled)
The following sections provide the timing and specifications for the entry and exit of these modes.
3.4.1
Power-On Timing
The external voltage regulator and other power-on devices must provide the JZ4730 processor with a specific sequence of power and resets to ensure proper operation. ? shows this sequence and is detailed in ?. On the processor, it is important that the power supplies be powered up in a certain order to avoid high current situations. The required order is: 1. VDDIO1 & VDDIO2 & VDDUSB 2. VDDCORE & VDDPLL
tr_VDDIO VDDIO1/VDDIO2 /VDDUSB VDDcore/VDDPLL tr_VDDCORE tD_VDDCORE tD_TRST_ tD_JTAG
TRST_ JTAG PINS
RESETP_ RESETOUT_
tD_RESETP_ tD_RESETOUT_
Figure 3-1 Power-On Timing Diagram
35 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Table 3-9 Power-On Timing Parameters Symbol tr_VDDIO tD_VDDCORE tr_VDDOCRE tD_TRST_ tD_JTAG tD_RESETP_ tD_RESETOUT_ Description VDDIO1/VDDIO2/VDDUSB Rise / Stabilization time Delay between VDDIO1/VDDIO2/VDDUSB stable and VDDCORE/VDDPLL applied VDDOCRE/VDDPLL Rise / Stabilization time Delay between VDDCORE, VDDPLL stable and JTAG reset TRST_ deasserted Delay between TRST_ deasserted and other JATG pins active Delay between VDDCORE, VDDPLL stable and RESETP_ deasserted Delay between RESETP_ deasserted and RESETOUT_ deasserted Min 0.01 0 0.01 10 10 0.2(1) 117.2 Typical - - - - - - - Max 100 - 100 - - - 117.3 Unit ms ms ms ns ns ms ms
3.4.2
Hardware Reset Timing
The timing sequences for input signals RESETP_ and output signals RESETOUT_, are shown in Figure 3-2 and Table 3-10, assumes the power supplies are stable at the assertion of RESETP_.
t ac_reset_
RESETP_
t fd_resetout_
RESETOUT_
t rd_resetout_
Figure 3-2 Hardware Reset Timing Diagram
Table 3-10 RESETP_ to RESETOUT_ Timing Parameters
36 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.
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Electrical Specifications
Symbol tac_RESETP_ tfd_RESETOUT_ trd_RESETOUT_
Description Minimum assertion time of RESETP_ Delay between RESETP_ Asserted and RESETOUT_ Asserted Delay between RESETP_ deasserted and RESETOUT_ deasserted
Min 0.2(1) 3 117.2
Typical - 7 -
Max - 20 117.3
Unit ms ns ms
3.5
Memory Bus and PCMCIA AC Specifications
This section provides the timing information for these types of memory:
* * *
SRAM / ROM / Flash Card interface (PCMCIA or Compact Flash) SDRAM
3.6
3.6.1 3.6.2 3.6.3 3.6.4
Peripheral Module AC Specifications
LCD Module Timing CIM Module Timing SPI Module Timing External DMA Request and Grant
37 JZ4730 32 Bits Microprocessor Data Sheet, Revision 1.0 Copyright(R) 2005-2007 Ingenic Semiconductor Co., Ltd. All rights reserved.

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